During a read operation in a conventional non-volatile storage cell, an operating current will flow through the cell for at least one of the two possible stored logic states. Assuming that collection of such cells within a register or array are accessed in parallel and that storage of a logic ‘1’ is equally as likely as a logic ‘0’, on average, half of all accessed cells will conduct current throughout a read operation. To avoid this undesired power consumption, non-volatile storage cells are generally read out only at certain events (e.g., power-up-reset) with their contents being copied into volatile memory elements (e.g., flip-flops or latches) that may be read continuously with negligible power consumption (i.e., without DC operating current). After the non-volatile data has been captured in volatile memory, the read operation within the non-volatile register or array is terminated to conserve power.
Unfortunately, the need for additional storage elements (i.e., the volatile storage elements) to make non-volatile data continuously available to downstream circuitry without power penalty requires circuit overhead and increased die size. Additionally, the non-volatile storage elements still consume substantial power during read operations. Further, additional circuits, such as sense-amplifiers and digital control circuitry, are typically required to retrieve data from the non-volatile storage cells and copy the data into the volatile counterparts. For example, the copy operation may require a state-machine and clock signals.
Another problem with the read-and-copy approach is that it delays the power-on-reset (POR) cycle, requiring circuitry for reading and copying the non-volatile data to be enabled and functional before the non-volatile data may be applied to control/configure analog or digital circuitry, generally meaning that such circuitry will not be available until after completion of the power-on-reset cycle. Worse, where the non-volatile data is needed for proper reset and/or initialization of analog or digital circuitry, an additional power-on-reset cycle (and corresponding circuitry for initiating and carrying out the additional POR) may be required, further delaying system readiness.